1. Field of the Invention
The present invention relates to a data output buffer circuit in a semiconductor memory device for externally outputting data read out from a memory cell, and more particularly to a data output buffer circuit capable of preventing increase of noise and decrease of response speed due to variation of power supply voltage.
2. Description of the Prior Art
General data output buffer circuits used in semiconductor memory devices such as Static Random Access Memories (SRAMs), Dynamic Random Access Memories (DRAMs) and Erasable and Programmable Read-Only Memories (EEPROMs) convert data of complementary metal-oxide-semiconductor (CMOS) logic level read out from a memory cell into data of transistor--transistor logic (TTL) level to output the converted data to an external logic circuit. The data output buffer circuit utilizes a MOS transistor having a large channel width to improve fan-out and response speed.
However, the conventional data output buffer circuit embodied with the MOS transistor having the wider channel has a disadvantage of noise which is increasing as a power supply voltage increases. The increase of noise is resulted from the fact that a voltage of an impulse noise signal is increased and a chattering period is lengthened due to a greater power supply voltage during the switching of the transistor.
In order to prevent the increase of noise due to the increase of the power supply voltage, a data output buffer circuit consisting of MOS transistors having a narrow channel width has been suggested.
The MOS transistor having the narrow channel width can mostly satisfy the response speed at a relatively large power supply voltage, while the response speed is significantly lowered at a relatively low voltage. The response speed of the conventional data output buffer circuit at the low voltage is lowered owing to a voltage of an output signal which is gradually increased or decreased.